Service
Video Platform FPGA Board for Live VR System
A technology that super-imposes 3D virtual images into one image in Real-time through the Multi-channel Camera Interface, and the final image is compressed to reduce data bandwidth and is used in a Real-time Virtual Reality (VR) system that enables multiple cameras to process images with one device.
The Hardware Platform used two large-capacity Field Programmable Gate Arrays (FPGA), each consisting of Xilinx Virtex7 and Altera Area10. Inside the FPGA, there is an input unit that receives and stores images input from an external camera at high speed, and the high-speed interface is input through HDMI 1.4, HDMI 2.0. The input image is stored in SODIMM DDR or Component DDR3 and subsequently compressed by VR image processing and H.264/H.265 Encoder. The compressed image is then transferred to the customer’s computer via USB 3.0. All of this is done in real time and most of the image processing and compression is operated by hardware implemented in HDL.
Design Features
- Left FPGA device: Xilinx Virtex 7
- Right FPGA device: Altera Arria 10
- SODIMM DDR3
- Two DDR3 components for Virtext 7 and Arria 10
- Two USB3.0 device to communicate between the external computer and FPGAs
- HDMI 2.0 interface to interface with sensors and display
Application example
The following system diagram be applied to the VR Live system.
- Up to 32 cameras
- Up to 120 frame rate
- Up to 12K resolution
- Up to 2 directional 3D (left-right at horizontal and vertical)
